cRIO FPGA Compilation Error : xilinx 21955

[Barbu]

Hi all, I tried to compiled my first "real" application today, and how unexpected in the NI world: it didn't work !I got myself a nice error message from xilinx : Regenerating IP...ERROR:coreutil - Failure to set parameters on core: Illegal combination: Port A   Width and Port A DepthERROR:coreutil - Failure to generate output productsERROR:coreutil - An error occurred while running Java. Please examine the   console or coregen log file for a specific IP related error.   If there is no specific error the problem may be due to memory limitations.   For more information please consult solution record 21955 available from:   http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21955Finished Regenerating.ERROR:sim:57 - Error found during generationThe xilinx page did not help me so far, and I don't find any reference of the "Illegal combination: Port A Width and Port A Depth" error which is probably the key to my situation.The app. is not so complex (yet) and make some use of the "Memory" objects... maybe it's about that.Anyway, I'll welcome any observation, advice (or solution) ;-)

[muks]

<a href="http://forums.ni.com/ni/board/message?board.id=170&amp;message.id=306810&amp;requireLogin=False" target="_blank">This</a> thread discusses something similar.You can contact aashish from ni.

[Aashish_M]

Hey Babu,
Are you using a bit depth of 1?
Xilinx doesn't support a depth of 1, as mentioned in the above linked post.

[Barbu]

Yeah, sorry for the duplicate topic. The `1 depth seemed to be the problem here :-/ Maybe this check should be added in the memory/fifo object configuration dialog in future realease of the LabVIEW FPGA Module :-)&nbsp;