PID (FPGA) Gain Values

[Stirl]

Hi folks, i´m using a PID-Module on the FPGA level. Now i want to get the system stabil. Usually the I-gain is a very small value (i.g. 0.005). But you get 1,2,3,... With the P-Gain is everything ok. It´s working.If i increase the I-Gain, the system is freaking out. So, i need smaller values.And the D-Gain has no influence of the system at all.Well, i know that the the FPGA system doesn´t accept fluent point values.From my point of view i must change something in the default option. But i dont know exactly what and which values i have to change.Do anybody have an idea what to do? Thanks a lot  Andi

[StevenA]

What version of LV are you using?  And, what PID function are you using?

[Stirl]

Hi, i´m using LabView 8.5.0.It´s the normal PID-Module which you can choose on the FPGA Level.The layout of the PID is attached.Cheers    Andi


PID.gif:
Loading Image...

[Michelle_B]

Can you please post the name of the VI that you are using? Thanks!

[danreb]

I have the same problem as you. In my case I think that the trouble is the sampling time (25ns) that is so small that almost any valour of the Ki constant make the system trip, and also because of that the derivative time is useless (also you can check to use 1/Ti, there are different ways of considering the PID constants). I started using other PID VI, I get it on a sample from NI (CRIO motor control, altough you don´t have a CRIO you can use that PID VI, it´s more complete). Maybe you have the same problems at the beggining with it, but you can change the values of the constant Ilim (this is the antiwindup value for the Ki constant) and things get much more better just with Ki=1. Things worked that way but I don´t really liked it.I finally decided to use my own PID algorithm, I´m still working on it, and by now I have the same troubles, but in the future I will scale the Ki, Kc and Td inside the FPGA module and decrease the PID sampling frecuency and hope everything starts to work fine at last.Best regards.

[Stirl]

Thanks for all the help. I tried a lot to get the system in a stabil run. I changed The normal PID with the Fixed Point PID. But this creates me a lot of noise.Well, now i went back to the normal PID module by only changing the Kc gain.I eliminate the offset by adding a value to the signal output.This works pretty good for my application. Cheers   Andi


PID Offset.pdf:
http://forums.ni.com/attachments/ni/170/342775/1/PID Offset.pdf

[Michelle_B]

Stirl, To get rid of the steady state error (I assume this is what you mean by offset), you should try increasing the Integral Gain (in other words decrease Integral Time).Does this makes sense? This Tutorial details the effect of chaging each gain in your PID system: <a href="http://zone.ni.com/devzone/cda/tut/p/id/6440" target="_blank">PID Control</a>.

[Stirl]

Thanks folks for the advices. I tried arround with all gains, including the sampling time.Now i got it in a stabil movement. What i not understand is, where is the difference between the sampling time Ts and the timer of the loop.In my system i want to move a piston with a linear motor. My program creates diffent kind of waves (sine, square, triangle).Each wave is discribed by 180 values and runs with max 10Hz. That means with max frequency, the stapoint frequency is 1.8kHz. (every 560 usec a new value).In my opinion the PID loop should run ten times faster. That doesnt work. I cant put this time in the PID module for Ts.I thik this value is for the calculations for I.Gain and D-Gain!? But running the loop with that time, the system (50usec) is unstabil....I am a little bit confuesd.The picture shows you my response of the system.


PID Ts.JPG:
http://forums.ni.com/attachments/ni/170/344291/1/PID Ts.JPG

[Stirl]

Hi again, i created another picture to make clear what my problem with the timer of the loop and the sampling time is.If i run the system i cant change the sampling time of the PID!? Or is the PID calculating with the timer of the loop when it runs?How can i define what 1 Tick is in real time? I´m not sure if my advicements are right.Thanks.&nbsp; Andi


Clock.JPG:
Loading Image...

[danreb]

Good morning, I think your main problem is that the sampling time is too high. Don´t know if the Ts on the PID vi is the real or an stimated sampling time in order to do a rescaling. Now I´m working with a PID to control a system drived by a DC motor and I had problems with the Ki gain. I don´t know if you have access to the integral part of the PID with that VI, but if you have it you can use an antiwind up strategy in order to reduce as much as possible the overshoot ot the system.Also, if it´s possible, try to use smaller sampling time (at least in the PID loop) to avoid the overshoot due to the integral part.Finally, you can check this sample <a href="http://zone.ni.com/devzone/cda/tut/p/id/6143" target="_blank">http://zone.ni.com/devzone/cda/tut/p/id/6143</a> . Maybe you aren´t using a CRIO, but you can use the PID VI in the FPGA VI, because it´s more complete than the one you are using, and it has an PID input (Ilim) to limit the integral effect so you could have better control of the system. Best regards.

[Stirl]

Hi, i think, now i understand whats going wrong with my system.You are right, my sampling time is to high. When your while loop runs faster than your sampling time of the fpga is, your system goes crazy.That makes sense, because the I-Gain is calculaiting during the P-gain is changing. The reason for that is that the in the calculations the Ts is missing.Unfortunately i cant use the antiwindup function on the FPGA.&nbsp; I will try to decrease the sampling time to 1e-5. If i´m succesful, i wil post it.But you helped me a lot... (we have really the same problems)Andi

[Stirl]

HI, my conclusion now is, that you cant set Ts (Sampling time) to less than 1ms. You can insert a smaller value, but it´s not running with it. In "Using the PID Software" stands, that the PID Control VI´s can execute at kHz rates.I will now program a logic which creates me for every amplitude an frequncy the right values to decimate my offset and which gives the motors the best performance.Therefor i have to test the system and note the values. Not the best way, but it is a simple and safety solution.Cheers&nbsp; Andi

[danreb]

Good morning. Actually, you can use sampling time less than 1ms. I use 20kHz of sampling time without problems (and I think I can go further with little changes of my VI, but I don´t need so much speed). I´m attaching you my PID solution. This is the algorithm of an PID with antiwindup. The good thing (for me) is the "Divisor Ki (2^n)". With that control, I can use decimal Ki, instead of just integer values. The fpga works with integer numbers, but dividing the integer part for 2^n I can use something like decimal values (first multiplicate and after divide for 2^n) and increasing the denominator, the integer part doesn´t trip.Also, I have implemented an antiwindup for the integer part (one of those coerced blocks) and a final saturation to have my maximun output value. With the divisor of the Ki I don´t need now the antiwindup, but I have implemented it because is easy and maybe I need it on the future.I had (think) the same problems that you have with the oscillation of the my system, but now with that algorithm it works fine changing the n value.Hope it helped, best regards.


PID.JPG:
Loading Image...

[Stirl]

Thanks for publishing your algorithm. I got now my system in a stable movement.I´m running out of time for this project so i cant implement your solution to test it. But may be in the future, the i will give you a feedback.Cheers &nbsp;&nbsp; Andi

[StevenA]

OK, this is the built in FPGA PID vi (new to LV 8.5).&nbsp; Take a look at the help screens.&nbsp; Double click on the PID express vi and read how the PID gains are implemented.
&nbsp;
This is the text right out of the help.

<a name="details" target="_blank">PID (FPGA) Details</a>

The Express VI represents the PID proportional, integral, and derivative gains as 16-bit integers, where the upper 8 bits represent the integer part and the lower 8 bits represent the fractional part. Given the Proportional gain (Kc), Integral time (Ti, min), and Derivative time (Td, min), respectively, the Express VI scales these gains according to the following formulas.

&nbsp;

[Michelle_B]

To add to this here are some general PID KnowledgeBases: <a href="http://zone.ni.com/devzone/cda/tut/p/id/3782" target="_blank">PID Theory Explained</a> and <a href="http://zone.ni.com/devzone/cda/tut/p/id/6440" target="_blank">PID Control </a> Hope this helps!

[danreb]

Good morning again. I don´t think it´s a good idea to do that (just adding the offset). I don´t think that it works in every point. Maybe if you have a constant countertorque (in case of motor control) or similar works, but I dont think it´s the best way to do it.You can try to decrement the frecuency of the PID calculations in order to avoid too much integrator effect or try to use an antiwindup limiter (I don´t know if you can use that PID VI has this option).I´m developing my own PID for that reason, the FPGA work rate is two much fast and it make the integrative component grown very fast and the system doesn´t works very well. By now I´m having good results with it.Best regards.